# Google’s expanded Marvell deal turns custom chips into a whole data center build

By MarketScale Newsroom · Published 2026-08-29 · Software & Technology on MarketScale
Canonical: https://www.marketscale.com/industries/software-and-technology/googles-expanded-marvell-deal-turns-custom-chips-into-a-whole-data-center-build

> Google’s expanded Marvell deal reaches past TPUs into NICs, storage and memory controllers, turning “custom silicon” into a procurement and platform decision.

## Key points

- Google's deal with Marvell now includes NICs, storage, and memory controllers.
- Custom silicon is becoming integral to the procurement strategy in data centers.
- The partnership reflects increased demand for tailored cloud computing solutions.

Google’s latest custom-silicon move is easy to misread as a single “AI chip deal.” It’s broader than that, and the structure tells operators what kind of procurement and platform conversations are coming next.

Marvell Technology disclosed an expanded partnership with Google that includes a warrant giving Google the option to buy up to 58,970,907 Marvell shares at $206.58 each, a stake worth as much as about $12.2 billion at the strike price, according to Marvell’s securities filing cited by CNBC and covered by the Financial Times. The warrant vests over time based on Google’s purchases of qualifying custom products, and the targets run through Marvell’s fiscal 2033, CNBC reported.

That’s the headline figure. The operational story is in what Marvell says it will build, and where those chips sit in the AI server.

## The scope reaches into networking, storage and memory controllers

EE Times reported Marvell has been unusually explicit about the engineering scope: the relationship encompasses AI inference accelerators, storage controllers, network interface controllers (NICs), memory-interface controllers and near-memory compute, extending well beyond Google’s tensor processing units (TPUs). CNBC also pointed to Marvell’s description that the expanded agreement covers products that “attach to the TPU ecosystem,” including inference accelerators and storage and network interface controllers.

For data center operators, this “attach” language matters. Accelerators are only part of what gets bought, racked, cabled and kept healthy. The rest of the AI node, the I/O path, memory subsystem and networking, increasingly decides whether expensive compute sits waiting on data.

> AI clusters are starting to be designed the way storage arrays used to be: the controller and the fabric decide what the expensive silicon can actually do.

EE Times cast the agreement as evidence that Google is pushing the TPU playbook further into AI data center design. The premise is that when purpose-built silicon lowers the cost of AI compute, it makes sense to extend that approach beyond matrix math to memory and data transport. The piece also noted Google did not publish a separate announcement, so Marvell’s SEC filings and earnings remarks are the primary public sources for specifics.

## The warrant structure is a public hint about long-horizon supply alignment

The warrant is not a standard, direct equity stake. EE Times reported it gives Google the right to buy nearly 59 million Marvell shares, with most of those shares vesting over time as Google purchases qualifying custom products. EE Times also reported that reaching full vesting corresponds to up to $120 billion of cumulative revenue through Marvell’s fiscal 2033, while stressing that this figure is a ceiling linked to full vesting, not a guaranteed buying obligation.

That structure is notable for enterprise procurement leaders because it puts a public marker on what hyperscalers are trying to buy with these arrangements: not only chip performance, but multi-year supply alignment and engineering priority. As custom silicon creeps into more parts of the AI stack, similar “economic alignment” features can show up around other strategic components, from advanced packaging partnerships to high-speed networking roadmaps.

## TPUs moving outside Google changes who has to care about the ecosystem

Financial Times reported the expanded partnership comes as Google begins selling TPUs, once largely used internally, to external customers. That matters because the surrounding silicon choices, the NICs, storage controllers and memory interfaces that make an accelerator usable at scale, become part of what customers evaluate, contract for and support.

EE Times also cited Futurum Group research director Brendan Burke’s view that the agreement is less about displacing existing TPU partners and more about adding custom programs around the TPU. In practice, that suggests a wider “Google-designed” footprint in the AI node over time, and more platform-level differentiation tied to data movement and memory behavior.

> If Google is customizing the chips around the accelerator, the real lock-in is in the data path, not the compute core.

CNBC noted Google has largely worked with Broadcom on custom chips over the last decade, and Financial Times said Broadcom is Google’s main supplier for its TPUs. For enterprise operators, the immediate implication isn’t vendor drama, it’s architectural: the AI platform conversation is widening from ‘which accelerator’ to ‘which end-to-end node design,’ including the attach silicon that drives compatibility, telemetry and upgrade cadence.

## Where this lands in specs and runbooks

This development won’t change a typical enterprise’s bill of materials overnight. But it does change what becomes “standard” in the market, especially if more TPU capacity is offered to customers and partners, as the Financial Times reported.

For teams running or planning AI clusters, the useful question is less whether custom silicon is good in the abstract, and more where custom controllers and NICs change day-2 operations: qualification testing, driver and firmware management, observability integration, and sparing strategy. If workloads are I/O-heavy (retrieval-augmented generation, multimodal pipelines, large embedding stores), the attach silicon can be the limiting factor long before the accelerator is saturated.

### Checks to add to TPU ecosystem evaluations this quarter

- Ask suppliers to provide a complete bill of materials for the full “TPU ecosystem,” specifying which NIC, storage-controller and memory-interface parts are standard in the reference design and which are optional or on the roadmap, using Marvell’s stated scope as the checklist (EE Times).
- Require clear lifecycle accountability for firmware and drivers tied to attach silicon: identify who signs and ships updates and how those releases are validated against your orchestration and observability stack.
- For RFPs that include TPUs, define performance requirements at both the accelerator and system levels: ask for throughput and latency results that pinpoint the source of any slowdown (network, storage, memory) so comparisons do not reduce to “TOPS vs TOPS.”
- For multi-year capacity plans, view long-horizon supplier alignment as a way to lower execution risk: the warrant-style structures described by CNBC and EE Times indicate that availability and priority are being contractually engineered, not assumed.

## Sources

- [Google’s Marvell Deal Shows Custom Silicon Spreading Beyond the TPU](https://www.eetimes.com/googles-marvell-deal-shows-custom-silicon-spreading-beyond-the-tpu/) (EE Times)
- [Marvell’s stock pops 10% on AI chip deal that lets Google buy up to $12.2 billion in shares](https://www.cnbc.com/2026/08/19/marvell-google-ai-chips.html) (CNBC)
- [Google strikes $12bn AI chip deal with Marvell](https://www.ft.com/content/0fdb094c-fc03-4d3c-8da6-bd11af88ff63?syn-25a6b1a6=1) (Financial Times)

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